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wideband, high output current fast settling op amp data sheet AD842 features ac p erformance gain bandwidth p roduct: 80 mhz (g ain = 2) fast s ettli ng: 100 ns to 0.01% for a 10 v s tep slew r ate: 375 v/ s stable at g ains of 2 or g reater full power b andwidth: 6 mhz for 20 v p - p dc p erformance input offset v oltage: 1 .5 mv max imum input offset d rift: 14 v/ c inpu t voltage n oise: 9 nv/hz op en - loop g ain: 90 v/mv into a 499 l oad output c urrent: 100 ma min imum quiescent supply c urrent: 14 ma max imum applications line d rivers dac and adc b uffers video and pulse a mplifiers mil - std - 883b parts a vailable , see military data s heet connection diagram s figure 1 . pdip (n - 14) and cerdip (q - 14) figure 2 . soic_w (rw - 16) general description the AD842 is a member of the analog devices , inc. family of wide bandwidth operational amplifiers. this device is fabricated using the analo g device junction isolated complementary bipolar (cb) process. this process permits a combination of dc precision and wideband ac performance previously unobtain - able in a monolithic op amp. in addition to its 80 mhz gain bandwidth product , the AD842 offers extremely fast settling characteris tics, typically settling to within 0.01% of final value in less than 100 ns for a 10 v step. the AD842 also offers a low quiescent current of 13 ma, a high output current drive capability (100 ma minimum), a low input voltage noise of 9 nvhz , and a low input offset voltage (1 .5 mv maximum). the 375 v/ s slew rate of the AD842 , along with its 80 mhz gain bandwidth product , ensures excellent performance in video and pulse amplifier applications. this amplifier is ideally suited for use in high frequency signal conditioning circuits and wide bandwidth active filters. the extremely rapid settling time of the AD842 makes this amplifier the preferred choice for data acquisition applications requiring 12- bit accuracy. the AD842 is also appropriate for other applications , such as high speed dac and adc buffer amplifiers and other wide bandwidth circuitry. product highlights 1. the high slew rate and fast settling time of the AD842 make it ideal for dac and adc buffers amplifiers , line drivers , and all types of video instrumentation circuitry. 2. the AD842 is a precisi on amplifier. it offers accuracy to 0.0 1% or better and wide bandwidth, performance previously available only in hybrids. 3. laser - wafer trimming reduce s the input offset voltage of 1 .5 mv max imum , thus eliminating the need for external offset nulling in many applications. 4. full differential inputs provide outstanding performance in all standard high frequency op amp applications where the circuit gain is 2 or greater. nic nic balance ?input +input v? nic nic balance nic v+ output nic nic + 1 2 3 4 14 13 12 1 1 5 6 7 10 9 8 notes 1. nic = not internal l y connected. AD842 t op view (not to scale) 09477-001 1 2 3 4 16 15 14 13 5 12 6 1 1 7 10 8 9 AD842 t o p view (not to scale) 09477-002 balance ?input nic +input nic ?v s nic balance +v s nic output nic nic nic + nic nic notes 1. nic = not internal l y connected. rev. f document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by an alog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent righ ts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 1988 C 2014 analog devices, inc. a ll rights reserved. technical support www.analog.com
AD842* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-402: replacing output clamping op amps with input clamping amps ? an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems ? an-581: biasing and decoupling op amps in single supply applications data sheet ? AD842: military data sheet ? AD842: wideband, high output current fast settling op amp data sheet tools and simulations ? power dissipation vs die temp ? vrms/dbm/dbu/dbv calculators reference materials tutorials ? mt-032: ideal voltage feedback (vfb) op amp ? mt-033: voltage feedback op amp gain and bandwidth ? mt-047: op amp noise ? mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth ? mt-049: op amp total output noise calculations for single-pole system ? mt-050: op amp total output noise calculations for second-order system ? mt-052: op amp noise figure: don't be misled ? mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr ? mt-056: high speed voltage feedback op amps ? mt-058: effects of feedback capacitance on vfb and cfb op amps ? mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to- voltage converters ? mt-060: choosing between voltage feedback and current feedback op amps design resources ? AD842 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all AD842 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
AD842 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 connection diagr ams ...................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical cha racteristics?15 v operation ............................ 3 absolute maximum ratings ............................................................ 4 thermal characteristics .............................................................. 4 esd caution .................................................................................. 4 metalization photo graph ............................................................. 4 typical performance characteristics ..............................................5 theory of operation .........................................................................9 offset nulling ................................................................................9 settling time ..................................................................................9 grounding and by passing ......................................................... 10 capacitive load driving ability ............................................... 10 using a heat sink ....................................................................... 10 terminated line driver ............................................................. 10 overdr ive recovery ................................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 13 revision history 2/14 rev. e to rev. f updated f ormat .................................................................. universal deleted 20 - terminal lcc and 12 - pin to - 8 .................. universal changed nc pin to nic pin throughout .................................... 1 changes to features, general description, connection diagrams, and product highlights sections ................................. 1 changes to table 1 ............................................................................ 3 changes to table 2 , thermal characteristics section, table 3, and figure 3 ....................................................................................... 4 changes to figure 11 , figure 13, figure 14, and figure 15 ........ 6 changes to figure 18 ......................................................................... 7 changes to figure 22 caption, figure 23 caption, figure 24, and figure 27 ...................................................................................... 8 changes to figure 28 ......................................................................... 9 changes to using a heat sink section and figure 32 ................ 1 0 changes to figure 34 ...................................................................... 1 1 updated outline dimensions ....................................................... 12 added ordering guide .................................................................. 1 3 3 /0 0 rev. d to rev. e rev. f | page 2 of 16
data sheet AD842 specifications electrical character istics 15 v operation t a = 25 c, unless otherwise specified. all min imum and max imum specifications are guaranteed. specifications shown in boldface are tested on all production units. table 1 . parameter test conditions / comments AD842 j n / AD842 jq / AD842 jr 1 AD842 k n / AD842 kq AD842 s q unit min typ max min typ max min typ max input offset voltage 2 0.5 1.5 0.3 1.0 0.5 1.5 mv t min to t max 2.5/2.5/3 1.5 3.5 mv offset drift 14 14 14 v/ c input bias current 4.2 8 3.5 5 4.2 8 a t min to t max 10 6 12 a input offset current 0.1 0.4 0. 0 5 0.2 0.1 0.4 a t min to t max 0.5 0.3 0.6 a input characteristics differential m ode input resistance 100 100 100 k input capacitance 2.0 2.0 2.0 pf input voltage range common mode 10 10 10 v common - mode rejection v cm = 10 v 86 115 90 115 86 115 db t min to t max 80 86 80 db input voltage noise f = 1 khz 9 9 9 nv/hz wideband noise 10 hz to 10 mhz 28 28 28 v rms open - loop gain v out = 10 v r load 499 40/40/30 90 50 90 40 90 v/mv t min to t max 20/20/15 25 20 v/mv output characteristics voltage r load 499 10 10 10 v current v out = 10 v 100 100 100 ma open l oop 5 5 5 frequency response gain bandwidth product v out = 90 mv , a vcl = 2 80 80 80 mhz full power bandwidth 3 v out = 20 v p - p , r load 499 4.7 6 4.7 6 4.7 6 mhz rise time a vcl = ?2 10 10 10 ns overshoot a vcl = ?2 20 20 20 % slew rate a vcl = ?2 300 375 300 375 300 375 v/s settling time 4 10 v step to 0.1% 80 80 80 ns to 0.01% 100 100 100 ns differential gain f = 4.4 mhz 0.015 0.015 0.015 % differential phase f = 4.4 mhz 0.035 0.035 0.035 degree power supply rated performance 15 15 15 v operating range 5 18 5 18 5 18 v quiescent current 13/13/14 14/14/16 13 14 13 14 ma t min to t max 16/16/19.5 16 19 ma power supply rejection ratio v s = 5 v to 18 v 86 100 90 105 86 100 db t min to t max 80 86 80 db 1 AD842 jr specifications differ from those of the AD842 jn and AD842 jq due to the thermal characteristics of the soic package . 2 input offset voltage specifications are guaranteed after 5 minutes at t a = 25 c. 3 full power bandwidth = slew rate/2 v peak. 4 re fer to figure 29 and figure 30. rev. f | page 3 of 16
AD842 data sheet absolute maximum rat ings table 2. parameter rating supply voltage 18 v internal power dissipation 1 pdip (n -14) , soic _w (rw -16) 1.3 w cerdip (q -14) 1.1 w input voltage v s differential input voltage 6 v operating temperature range cerdip ( q - 14, AD842 sq only) ?55c to +125c pdip (n -14), soic_w (rw -16), cer dip ( q-14, AD842 jq and AD842 kq only ) 0c to 70c storage temperature range cerdip (q -14 , all models ) ?65c to +150c pdip (n - 14) , soic_w (rw - 16 ) ?65c to +125c junction temperature 175c lead temperature (soldering 60 sec) 300c 1 maximum internal power dissipation is specified so that t j does not exceed 150 c at an ambient temperature of 25 c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics table 3. package jc ja sa unit 14- lead pdip 30 100 c/w 14- lead cerdip 30 110 38 c/w 16- lead soic_w 30 100 c/w esd caution metalization photogr aph figure 3 . contact factory for latest d imensions, dimensions shown in inches and (m illimeters) output v+ v? 0.067 (1.69) balance 0.106 (2.68) balance +input ?input 09477-003 rev. f | page 4 of 16
data sheet AD842 typical performance characteristics t a = 25c and v s = 15 v, unless otherwise noted . figure 4. input common - mode range vs. supply voltage figure 5. output voltage swing vs. supply voltage figure 6. output voltage swing vs. load resistance figure 7. quiescent current vs. supply voltag e figure 8. input bias current vs. temperature figure 9. output impedance vs. frequency supply voltage (v) input common-mode range (v) 20 15 0 20 15 10 5 0 10 5 v in 09477-004 supply voltage (v) output voltage swing (v) 20 15 0 20 15 10 5 0 10 5 v out 09477-005 load resistance (?) output voltage swing (v p-p) 30 25 0 10k 100 10 1k 20 15 5 10 15v supplies 09477-006 supply voltage (v) quiescent current (ma) 18 16 10 20 15 10 5 0 14 12 09477-007 temperature (c) input bias current (a) ?5 ?4 ?2 ?60 ?40 ?20 0 20 140 120 100 80 60 40 ?3 09477-008 frequency (hz) output impedance (?) 100 10 0.01 100m 10m 100k 1m 10k 1 0.1 09477-009 rev. f | page 5 of 16
AD842 data sheet figure 10 . quiescent current vs. temperature figure 11 . short - circu i t current limit vs. temperature figure 12 . gain bandwidth product vs. temperature figure 13 . open - loop gain and phase margin vs. frequency figure 14 . open - loop gain vs. supply voltage figure 15 . power supply rejection vs. frequency temperature (c) quiescent current (ma) 18 15 10 17 16 13 11 14 12 ?60 ?40 ?20 0 20 140 120 100 80 60 40 09477-010 temperature (c) short-circuit current limit (ma) 300 225 100 275 250 175 125 200 150 ?output current +output current ?60 ?40 ?20 0 20 140 120 100 80 60 40 09477-0 1 1 gain bandwidth (mhz) 85 80 65 75 70 temperature (c) ?60 ?40 ?20 0 20 140 120 100 80 60 40 09477-012 frequency (hz) open-loop gain (db) 120 0 100m 100 1k 10k 100k 1m 10m 100 80 60 40 20 100 80 60 40 20 0 phase margin (degrees) 499? load 09477-013 supply voltage (v) open-loop gain (db) 110 105 90 20 15 10 5 0 100 95 09477-014 499? load frequency (hz) power supply rejection (db) 120 0 100m 100 1k 10k 100k 1m 10m 100 80 60 40 20 09477-015 ?v s +v s rev. f | page 6 of 16
data sheet AD842 figure 16 . common - mode rejection vs. frequency figure 17 . large signal frequency response figure 18 . output swing vs. settling time figure 19 . harmonic distortion vs. frequency figure 20 . input voltage vs. frequency figure 21 . slew rate vs. temperature frequency (hz) common-mode rejection (db) 120 20 100m 1k 10k 100k 1m 10m 100 80 60 40 09477-016 v s = 15v v cm = 1v p-p t a = 25c frequency (hz) output voltage (v p-p) 30 25 0 1m 10m 100m 20 15 10 5 r l = 1k? t a = 25c v s = 15v 09477-017 settling time (ns) output swing (v) 10 ?10 110 40 50 60 70 80 90 100 30 8 2 0 ?4 ?8 6 4 ?2 ?6 0.1% 0.1% 0.01% 0.01% 09477-018 frequency (hz) harmonic distortion (db) ?80 ?90 ?140 100 1k 10k 100k ?100 ?110 ?130 ?120 second harmonic 09477-019 third harmonic 3v rms r l = 1k? frequency (hz) input voltage (nvhz) 50 40 0 10 100 1k 10k 100k 1m 10m 30 20 10 09477-020 slew rate (v/s) 550 400 250 500 450 350 300 temperature (c) ?60 ?40 ?20 0 20 140 120 100 80 60 40 09477-021 rev. f | page 7 of 16
AD842 data sheet figure 22 . inverting large signal pulse response (see figure 24 ) figure 23 . inverting small signal pulse response (see figure 24 ) figure 24 . inverting amplifier configuration (pdip) figure 25 . noninverting large signal pulse response (see figure 27 ) figure 26 . noninverting small signal pulse response (see figure 27 ) figure 27 . noninverting amplifier configuration (pdip) 09477-022 100% 90% 0% 10% 2v 50ns 09477-023 100% 90% 0% 10% 50mv 50ns +v s ?v s v out 499? 332? 2.2f 0.1f 2.2f 0.1f function generator r in = 499? r f = 1k? AD842 11 6 10 4 5 49.9? 09477-026 09477-024 100% 90% 0% 10% 2v 50ns 09477-025 100% 90% 0% 10% 50mv 50ns +v s ?v s v out 499? 2.2f 0.1f 2.2f 0.1f function generator 100? r f = 205? r f = 205? v in AD842 11 6 10 4 5 49.9? 09477-027 rev. f | page 8 of 16
data sheet AD842 theory of operation offset nulling the input offset voltage of the AD842 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in figure 28 can be used. settling time figure 29 and figure 31 show the settling performance of the AD842 in the test circuit shown in figure 30. settling time is t he interval of time from the application of an ideal step function input until t he closed - loop amplifier output enters and remains within a specified error band. this definition encompasses the major components that comprise settling time. they include the following : ? p ropagati on delay through the amplifier. ? s lewing time to approach the final output value. ? time of recovery from the overl oad associated with slewing. ? l inear settling to within the specified error band. expressed in these terms, the measurement of settling time must be accurate to assure the user that the amplifier is worth consideration for the application. figure 28 . offset nulling ( pdip ) figure 29 . 0.01% settling time figure 30 shows how measurement of the AD842 0.01% settling in 100 ns is accomplished b y amplifying the error signal from a false summing junction with a very high speed proprietary hybrid error amplifier specially designed to enable testing of sm all settling errors. under test, the device drives a 300 load . the input to th e error amp is c lamped to avoid possible problems associated with the overdrive recovery of the oscilloscope input amplifier. the error amp gains the error from the false summing junction by 15, and it contains a gain vernier to fine trim the gain. figure 31 shows the long - term stability of the settling characteristics of the AD842 output after a 10 v step. there is no evidence of settling tails after the initial transient recovery time. the use of a junction isolated process, together with careful layout, avoids these problems by minimizing the effects of transistor isolation capac itance discharge and thermally induced shifts in circuit operating points. these problems do not occur even under high output current conditions. figure 30 . settling time test circuit (pdip) +v s ?v s v out r l 2.2f 0.1f 2.2f 0.1f n? v in AD842 11 3 13 6 10 4 5 09477-028 09477-029 100% 90% 0% 10% 10mv 10v 20ns output: 10v/div output error: 0.02%/div 2.2f 0.1f 2.2f 0.1f ? ? ?15v ddd5109 flat-top pulse generator ? ? n? ? n? +15v hp6263 error amp (15) tek 7603 oscilloscope tek 7a13 tek 7a16 fet probe tek p6201 AD842 11 6 10 4 5 09477-030 rev. f | page 9 of 16
AD842 data sheet grounding and bypassing in designing practical circuits with the AD842 , the user must take some special precautions whenever high frequencies are involved. figure 31 . AD842 settling demonstrating no settling tails circuits must be built with short interconnect leads. use l arge ground planes whenever possible to provide a low resistance, low inductance circuit path ; this also minimize s the effe cts of high frequency coupling. avoid sockets because the increased interlead capacitance can degrade bandwidth. use f eedback resistors of low enough value to ensure that the time constant formed wit h the circuit capacitances does not limit the amplifier performance. resistor values of less than 5 k are recommended. if a larger resistor must be used, a small (<10 pf) feedback capacitor connected in parallel with the feedback resistor, r f , can be used to compensate for these stray capacitances and to optimize the dynamic performance of the amplifier in the particular application. bypass p ower supply leads to ground as close as possible to the amplifier pins. a 2.2 f capacitor in parallel with a 0.1 f ceramic disk capacitor is recommended. capacitive load driv ing ability like all wideband amplifiers, the AD842 is sensitive to capacitive loading. the AD842 is designed to drive capacitive loads of up to 20 pf without degradation of its rated performance. capacitive loads of greater than 20 pf decrease the dynamic performance of the device , although instability does not occur unless the load exceeds 100 pf. using a heat sink the AD842 draws less quiescent power than most precision high speed amplifiers and is specified for operation without a heat sink. however, when driving low impedance loads, t he current to the load can be 10 ti mes the quiescent current. this create s a noticeable temperature rise. use of a small heat sink improves performance . terminated line driv er the AD842 is optimized for high speed line driver applications. figure 32 shows the AD842 driving a doubly terminated cable in a gain - of - 2 follower configuration. the AD842 maintains a typical slew rate of 375 v/ s, which means it can drive a 10 v, 6 .0 mhz signal , or a 3 v, 19 .9 mhz signal. the termination resistor, r t , minimizes reflections from the far end of the cable when equal to the characteristic impedance of the cable . a back - termination resistor (r bt , also equal to the characteristic impedance of the cable) can be placed between the AD842 output and the cable to damp any stray signal s caused by a mismatch between r t and the characteristic impedance of the cable . this configuration results in a cleaner signal. with this circuit, the voltage on the line equals v in because one half of v out is dropped across r bt . the AD842 has a 100 ma minimum output current and, therefore, can drive 5 v into a 50 cable. choose t he feedback resistors, r1 and r2, carefully. large value resistors are desirable to limit the amount of current drawn from the a mplifier output. l arge resistors can cause amplifier instability because the parallel resistance of r1 || r2 combines with the input capacitance (typically 2 pf to 5 pf) to create an additional pole. the voltage noise of the AD842 is equivalent to a 5 k resistor; these large resistors can significantly increase the system noise. resistor values of 1 k or 2 k are recommended. if termination is not used, cables appear as capacitive loads and can be decoupled from the AD842 by a resistor in series with the output. figure 32 . line driver configuration (pdip) 09477-031 100% 90% 0% 10% 5mv 2s output: 5v/div output error: 0.01%/div 2.2f 0.1f 50? or 75? cable r t = r bt = cable characteristic impedance 2.2f 0.1f r1 r2 ?v s +v s v in AD842 11 6 10 4 5 4 r t r bt termination resistor for input signal 09477-032 rev. f | page 10 of 16
data sheet AD842 overdrive recovery figure 33 shows the overdrive recovery capability of the AD842 . typical recovery time is 80 ns from negative overdrive and 400 ns from positive overdrive. figure 33 . overdrive recovery figure 34 . overdrive recovery test circuit (pdip) 09477-033 100% 90% 0% 10% 10v 1v 100ns overdriven output: 10v/div input square wave: 1v/div +v s ?v s v out 1k? 50? 2.2f 0.1f 2.2f 0.1f pulse generator 1s, 1v square wave input AD842 11 6 10 4 5 09477-034 rev. f | page 11 of 16
AD842 data sheet outline dimensions figure 35 . 14 - lead plastic dual in - line package [pdip] narrow body (n - 14) di mensions shown in inches and (m illimeters) figure 36 . 14 - lead ceramic dual in - line package [cerdip] (q - 14) di mensions shown in inches and (millimeters) compliant t o jedec s t andards ms-001 controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. corner leads m a y be configured as whole or half leads. 070606- a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 10 (2.79) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) 14 1 7 8 0.100 (2.54) bsc 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.210 (5.33) max sea ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 0.310 (7.87) 0.220 (5.59) 0.005 (0.13) min 0.098 (2.49) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200 (5.08) max 0.785 (19.94) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) pin 1 1 7 8 14 rev. f | page 12 of 16
data sheet AD842 figure 37 . 16 - lead standard small outline package [soic_w] wide body (r w - 16) di mensions shown in inches and (millimeters ) ordering guide model 1 temperature range package description package option AD842jnz 0c to 70c 14 - lead plastic dual in - line package [pdip] n -14 AD842jq 0c to 70c 14 - lead ceramic dual in - line package [cerdip] q - 14 AD842kq 0c to 70c 14 - lead ceramic dual in - line package [cerdip] q -14 AD842jr -16 0c to 70c 16 - lead standard small outline package [soic_w] rw -16 AD842jrz -16 0c to 70c 16 - lead standard small outline package [soic_w] rw -16 AD842knz 0c to 70c 14 - lead plastic dual in - line package [pdip] n -14 AD842schips die AD842sq ?55c to +125c 14 - lead ceramic dual in - line package [cerdip] q -14 1 z = rohs compliant part. controlling dimensions are in milli mete rs; inch dimen sions (in p arentheses) are round ed-of f milli meter equiv alen ts for refer ence onl y and are not appro pria te for use in design. compl iant t o jedec st andards ms-013-aa 10.50 (0.4 134) 10.10 (0.39 76) 0.30 (0.01 18) 0.10 (0.00 39) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.41 93) 10.00 (0.39 37) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.02 95) 0.25 (0.009 8) 45 1.27 (0.0500) 0.40 (0.0157) copla narit y 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) sea ting plane 8 0 1 6 9 8 1 1.27 (0.05 00) bsc 03-27- 2007-b rev. f | page 13 of 16
AD842 data sheet notes rev. f | page 14 of 16
data sheet AD842 notes rev. f | page 15 of 16
AD842 data sheet notes ? 1988 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09477 - 0 - 2/14(f) rev. f | page 16 of 16

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